View PIC16F62X02_4779844.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PIC16F62X
PIC16F62X Silicon/Data Sheet Errata
The PIC16F62X (Rev. A) parts you have received conform functionally to the Device Data Sheet (DS40300B), except for the anomalies described below. 1. Module: I/O Ports A read of the PORTB Data Direction Register (TRISB) returns the Data Direction state on the port pins themselves and not the contents of the TRISB register latch.
FIGURE 1:
BLOCK DIAGRAM OF RB0/INT PIN
VDD RBPU VDD Weak P Pull-up
RB0/INT pin Data Bus D Q VSS CK Data Latch
WR PORTB
D WR TRISB
Q TTL Input Buffer
CK TRIS Latch
Schmitt Trigger Buffer
RD TRISB Q D EN EN
RD PORTB INT Input
(c) 2002 Microchip Technology Inc.
DS80073F-page 1
PIC16F62X
FIGURE 2: BLOCK DIAGRAM OF RB1/TX/DT PIN
VDD RBPU P Weak Pull-up Port/Peripheral Select USART Data Output
(1)
0 VDD 1 D WR PORTB Q Q P VDD
Data Bus
CK
Data Latch D WR TRISB Q Q N VSS VSS RB1/RX/DT pin
CK
TRIS Latch
RD TRISB Peripheral OE(2) Q RD PORTB EN USART Receive Input D
TTL Input Buffer
Schmitt Trigger
RD PORTB
Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only active if peripheral select is active.
DS80073F-page 2
(c) 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 3: BLOCK DIAGRAM OF RB2/TX/CK PIN
RBPU
VDD P Weak Pull-up
Port/Peripheral Select(1) USART TX/CK Output 0 VDD 1 Data Bus WR PORTB D Q Q P
VDD
RB2/TX/CK pin
CK
VSS Data Latch D WR TRISB Q Q N Vss
CK
TRIS Latch
RD TRISB Peripheral OE(2) Q RD PORTB EN EN USART Slave Clock In D
TTL Input Buffer
Schmitt Trigger
RD PORTB
Note 1: Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only active if peripheral select is active.
(c) 2002 Microchip Technology Inc.
DS80073F-page 3
PIC16F62X
FIGURE 4: BLOCK DIAGRAM OF THE RB3/CCP1 PIN
VDD RBPU P Weak Pull-up Port/Peripheral Select(1) PWM/Compare Output 0 VDD 1 Data Bus WR PORTB D Q Q P VDD
CK
Data Latch D WR TRISB Q N VSS TRIS Latch Vss RB3/CCP1 pin
CK
Q
RD TRISB
TTL Input Buffer Q D EN EN
RD PORTB
CCP Input
Schmitt Trigger
RD PORTB
Note 1: Peripheral select is defined by CCP1M3:CCP1M0 (CCP1CON<3:0>).
DS80073F-page 4
(c) 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 5: BLOCK DIAGRAM OF RB4/PGM PIN
VDD RBPU P Weak Pull-up
VDD Data Bus WR PORTB D Q Q P VDD
CK
Data Latch D WR TRISB Q Q N VSS TRIS Latch VSS RB4/PGM
CK
RD TRISB LVP
RD PORTB
PGM Input Schmitt Trigger TTL Input Buffer Q D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
Note 1: The Low Voltage Programming disables the interrupt-on-change and the weak pull-ups on RB4.
(c) 2002 Microchip Technology Inc.
DS80073F-page 5
PIC16F62X
FIGURE 6: BLOCK DIAGRAM OF RB5 PIN
VDD RBPU Weak P Pull-up VDD
Data Bus
D
Q RB5 pin
WR PORTB
CK Data Latch VSS D Q
WR TRISB
CK TRIS Latch TTL Input Buffer
RD TRISB Q RD PORTB EN Set RBIF D Q1
From other RB<7:4> pins
Q
D RD Port EN Q3
DS80073F-page 6
(c) 2002 Microchip Technology Inc.
PIC16F62X
FIGURE 7: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD RBPU P Weak Pull-up VDD Data Bus WR PORTB D Q Q P
VDD
CK
Data Latch D WR TRISB Q Q N VSS TRIS Latch VSS RB6/ T1OSO/ T1CKI pin
CK
RD TRISB T1OSCEN TTL Input Buffer
RD PORTB
TMR1 Clock
From RB7 Serial Programming Clock
Schmitt Trigger TMR1 Oscillator
Q
D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
(c) 2002 Microchip Technology Inc.
DS80073F-page 7
PIC16F62X
FIGURE 8: BLOCK DIAGRAM OF THE RB7/T10SI PIN
VDD RBPU P Weak Pull-up To RB6 T1OSCEN VDD VDD Data Bus WR PORTB D Q Q P RB7/T1OSI pin TMR1 Oscillator
CK
Data Latch D WR TRISB Q Q N Vss VSS
CK
TRIS Latch
RD TRISB T10SCEN
RD PORTB
TTL Input Buffer
Serial Programming Input
Schmitt Trigger Q D Q1
EN Set RBIF
From other RB<7:4> pins
Q
D RD Port EN Q3
DS80073F-page 8
(c) 2002 Microchip Technology Inc.
PIC16F62X
2. Module: Comparator Mode 1 Mode 1 allows AN2 to drive the (+) inputs of both comparators. AN1 continues to drive the (-) input of Comparator 2, but AN0 and AN3 can be switched into the (-) input of Comparator 1. The state of the CIS bit chooses which input is to be connected to the comparator. When CIS = 0, AN0 is attached and the comparator functions correctly. When CIS = 1, AN3 is not completely connected to the comparator, resulting in incorrect behavior. Mode 2 is also a Multiplex mode using the CIS bit. This mode functions correctly. All other modes are unaffected by this Errata. 3. Module: Low Voltage Programming Mode The high voltage override for low voltage programming does not operate as specified in the programming specification. In the Low Voltage Programming (LVP) mode, the device can be programmed without using 12V on VPP (pin 4). However, when high voltage programming is used while the part has low voltage programming enabled, the Low Voltage mode is not overridden. If RB4 goes high for any reason during high voltage programming with LVP enabled, the programming will be interrupted. Work around Pull RB4 (pin 10) to ground during the initial programming to prevent programming interruptions. Once LVP has been disabled, it remedies this issue with RB4. 4. Module: CCP (Compare Mode) The CCP1 output latch, observed on RB3/CCP1/ P1A, can change unexpectedly when the CCP module is changed from a set output on match (CCP1CON<3:0> = "1000") to clear output on match (CCP1CON<3:0> = "1001") or vice versa. This condition will occur following a CCP Reset at the beginning of the third iteration of the following sequence. * CCPR1<3:0> is changed from "1001" to "1000" or vice versa. * The TMR1H:TMR1L register pair matches the CCP1R1H:CCPR1L register pair. Step 1 of the third iteration will cause the CCP1 output latch to immediately and erroneously change to the inverse of the CCPR1<0> bit. This gives the appearance of an inverted CCP response to the third and subsequent compare match events. The apparent inverted response will persist until the CCP1CON<3> bit is cleared (exiting Compare mode). Interrupts always occur correctly on the match condition. The error is only in the state of the CCP1 output latch. Work around Option 1 Use the CCP toggle output on Compare Match mode (CCP1CON<3.0> = "0010"). Option 2 Since the problem occurs after two changes to the Compare and Match mode, it is only necessary to reset the CCP1CON register before the third change is made. To remain backwards compatible with earlier versions of the CCP module, always reset the CCP1CON register when changing from the clear output on Match mode to the set output on Match mode, as described in the following steps. 1. 2. 3. 5. Ensure the RB3 data latch is set to 0. Clear the CCP1CON register (clrf CCP1CON). Set the CCP1CON<3:0> bits to "1000" for set output on match.
Module: MCLR/RA5 in LVP Mode When the PIC16F62X device has LVP enabled, MCLR is always enabled, regardless of the CONFIG register settings.
(c) 2002 Microchip Technology Inc.
DS80073F-page 9
PIC16F62X
Clarifications/Corrections to the Data Sheet:
In the Device Data Sheet (DS40300B), the following clarifications and corrections should be noted. 1. Module: T1SYNC (Register T1CON) The bit T1SYNC in the Register T1CON (address 10h) should be asserted logic low (i.e., T1SYNC). Table 4-1, page 15, and Table 10-2, page 65, of DS40300B should be listed as follows: 2. Module: ADEN (Register RCSTA) The bit ADEN in Register RCSTA (address 18h), Table 4-1, is misspelled. The correct spelling should be ADDEN. This also appears in Figures and text on pages 72, 79, 80, 81, 82, 83, 84, 85, 86 and 89.
TABLE 4-1:
Address Name
SPECIAL REGISTERS SUMMARY BANK0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other RESETS(1)
Bank 0 10h T1CON -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 -00x 0000 -00x Legend: x = unknown, u = unchanged, - = unimplemented locations, read as `0', q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) RESETS include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
TABLE 10-2:
Address 10h Legend:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Bit 7 -- Bit 6 -- Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other RESETS
Name T1CON
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.
DS80073F-page 10
(c) 2002 Microchip Technology Inc.
PIC16F62X
17.1 DC Characteristics: PIC16F62X-04 (Commercial, Industrial, Extended) PIC16F62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Characteristic Supply Voltage RAM Data Retention Voltage VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Brown-out Detect Voltage Supply Current(2)
(1)
DC Characteristics
Param No. D001 D002 D003 D004 D005 D010 D013
Sym VDD VDR VPOR SVDD VBOD IDD
Min 3.0 -- -- 0.05* 3.65 3.65 -- -- -- -- -- -- -- -- -- -- -- -- -- --
Typ -- 1.5* Vss -- 4.0 -- -- -- 4.0 -- -- -- -- -- -- -- 6.0 75 30
Max 5.5 -- -- -- 4.35 4.4 0.7 2.0 7.0 6.0 2.0 10 2.2 5.0 9.0 30.0 20 25 125 50 135
Units V V V
Conditions
Device in SLEEP mode See section on Power-on Reset for details
V/ms See section on Power-on Reset for details V V mA mA mA mA mA A A A A A A A A A A BODEN configuration bit is set BODEN configuration bit is set, Extended FOSC = 4.0 MHz, VDD = 3.0 FOSC = 4.0 MHz, VDD = 5.5* FOSC = 20.0 MHz, VDD = 5.5 FOSC = 20.0 MHz, VDD = 4.5* FOSC = 10.0 MHz, VDD = 3.0*, Commercial FOSC = 32 kHz, VDD = 3.0* VDD = 3.0, Commercial, Industrial VDD = 4.5*, Commercial, Industrial VDD = 5.5, Commercial, Industrial VDD = 5.5, Extended VDD = 4.0V, Commercial, Industrial VDD = 4.0V, Extended BOD enabled, VDD = 5.0V VDD = 4.0V VDD = 4.0V
D014 D020 IPD Power-down Current(3)
D022
IWDT
WDT Current(4) Brown-out Detect Current(4) Comparator Current for each Comparator(4) VREF Current(4)
D022A IBOD D023 ICOMP D023A IVREF *
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT disabled. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
(c) 2002 Microchip Technology Inc.
DS80073F-page 11
PIC16F62X
17.2 DC Characteristics: PIC16LF62X-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial Operating voltage VDD range as described in DC spec Table 17-1 and Table 12-2 Characteristic Supply Voltage RAM Data Retention Voltage VDD start voltage to ensure Power-on Reset VDD rise rate to ensure Power-on Reset Brown-out Detect Voltage Supply Current(2)
(1)
DC Characteristics
Param No. D001 D002 D003 D004 D005 D010 D013
Sym VDD VDR VPOR SVDD VBOD IDD
Min 2.0 -- -- 0.05* 3.65 -- -- -- -- -- -- -- -- -- -- -- --
Typ -- 1.5* Vss -- 4.0 -- -- 4.0 -- -- -- -- -- 6.0 75 30
Max 5.5 -- -- -- 4.35 0.6 0.7 7.0 6.0 2.0 TBD 1.98 9.0 15 125 50 135
Units V V V
Conditions
Device in SLEEP mode See section on Power-on Reset for details
V/ms See section on Power-on Reset for details V mA mA mA mA mA A A A A A A A BODEN configuration bit is cleared FOSC = 4.0 MHz, VDD = 2.0 FOSC = 4.0 MHz, VDD = 5.5* FOSC = 20.0 MHz, VDD = 5.5 FOSC = 20.0 MHz, VDD = 4.5* FOSC = 10.0 MHz, VDD = 3.0, Commercial FOSC = 32 kHz, VDD = 2.0* VDD = 2.0 VDD = 5.5 VDD = 3.0V BOD enabled, VDD = 5.0V VDD = 3.0V VDD = 3.0V
D014 D020 D022 D022A D023 D023A * IPD IWDT IBOD ICOMP IVREF Power-down Current(2), (3) WDT Current(4) Brown-out Detect Current(4) Comparator Current for each Comparator(4) VREF Current(4)
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS. 4: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement.
DS80073F-page 12
(c) 2002 Microchip Technology Inc.
PIC16F62X
17.3 DC Characteristics: PIC16F62X (Commercial, Industrial, Extended) PIC16LF62X (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial and 0C TA +70C for commercial and -40C TA +125C for extended Operating voltage VDD range as described in DC spec Table 17-1 and Table 12-2 Min Typ Max Unit Conditions
DC Characteristics
Param. No.
Sym
VIL
Characteristic
Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger input MCLR, RA4/T0CKI,OSC1 (in ER mode) OSC1 (in XT and HS) OSC1 (in LP)
D030 D031 D032 D033 VIH D040 D041 D042 D043 D070 IPURB IIL
VSS VSS VSS VSS VSS
--
0.8 0.15 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.6 VDD-1.0
V V V V V
VDD = 4.5V to 5.5V otherwise
-- -- -- --
Input High Voltage I/O ports: with TTL buffer with Schmitt Trigger input MCLR RA4/T0CKI OSC1 (EC mode) OSC1 (XT, HS and LP) PORTB weak pull-up current Input Leakage I/O ports (except PORTA) PORTA RA4/T0CKI OSC1, MCLR Current(1), (2) 1.0 A A A A VSS VPIN VDD, pin at hi-impedance VSS VPIN VDD, pin at hi-impedance VSS VPIN VDD VSS VPIN VDD, XT, HS and LP osc configuration IOL=8.5 mA, VDD=4.5V, -40 to +85C IOL=7.0 mA, VDD=4.5V, +125C IOL=1.6 mA, VDD=4.5V, -40 to +85C IOL=1.2 mA, VDD=4.5V, +125C IOH=-3.0 mA, VDD=4.5V, -40 to +85C IOH=-2.5 mA, VDD=4.5V, +125C IOH=-1.3 mA, VDD=4.5V, -40 to +85C IOH=-1.0 mA, VDD=4.5V, +125C RA4 pin PIC16F62X, PIC16LF62X 2.0V .25 VDD + 0.8V 0.8 VDD 0.8 VDD 0.8 VDD 0.7 VDD 50 -- -- -- -- -- 200 VDD VDD VDD VDD VDD VDD 400 V V V A VDD = 5.0V, VPIN = VSS V VDD = 4.5V to 5.5V otherwise
D060 D061 D063 VOL D080 D083
-- -- --
-- -- --
0.5 1.0 5.0
Output Low Voltage I/O ports OSC2/CLKOUT (ER only) Output High Voltage(2) I/O ports (except RA4) OSC2/CLKOUT (ER only) VDD-0.7 VDD-0.7 VDD-0.7 VDD-0.7 -- -- -- -- -- -- -- -- -- 8.5* V V V V V -- -- -- -- -- -- -- -- 0.6 0.6 0.6 0.6 V V V V
VOH D090 D092 *D150 VOD
Open Drain High Voltage Capacitive Loading Specs on Output Pins
D100 D101 * Note 1: 2:
COSC2 OSC2 pin CIO All I/O pins/OSC2 (in ER mode)
-- --
15 50
pF pF
In XT, HS and LP modes when external clock used to drive OSC1
These parameters are characterized but not tested. Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as coming out of the pin.
(c) 2002 Microchip Technology Inc.
DS80073F-page 13
PIC16F62X
3. Module: I/O Ports (RA5/MCLR/VPP) The following block diagram shown in Section 5, Figure 5-5 is incorrect. The following figure should be used instead.
FIGURE 5-5:
BLOCK DIAGRAM OF THE RA5/MCLR/VPP PIN
MCLRE MCLR Circuit MCLR Filter(1) VDD
Program Mode
HV Detect RA5/MCLR/VPP
VSS
Data Bus
Q
D
EN RD Port
DS80073F-page 14
(c) 2002 Microchip Technology Inc.
PIC16F62X
4. Module: Comparator The example given in Section 9, Example 9-1, concerning "Initializing the Comparator Module" is incorrect. The following code example should be used instead.
EXAMPLE 9-1:
BCF BCF CLRF MOVLW MOVWF BSF MOVLW MOVWF
INITIALIZING COMPARATOR MODULE
INTCON,GIE INTCON,PEIE PORTA 0X03 CMCON STATUS,RP0 0x07 TRISA ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Turn OFF Global Interrupts Turn OFF Peripheral Interrupts Init Port A Init comparator mode CM<2:0> = 011 Select BANK 1 Initialize Port A Direction Set RA<2:0> as Inputs RA<4:3> as outputs TRIS<5> always reads '0' Select BANK 0 Wait 10us for comparator output to become valid See Table 17-1 Parameter 301 Read CMCON to end change condition Clear pending interrupts Select BANK 1 Enable Comparator Interrupts Select BANK 0 Enable Peripheral Interrupts Global Interrupt Enable
BCF CALL MOVF BCF BSF BSF BCF BSF BSF
STATUS,RP0 DELAY10 CMCON,F PIR1,CMIF STATUS,RP0 PIE1,CMIE STATUS,RP0 INTCON,PEIE INTCON,GIE
; Insert Your code.... ; Helper function is the Delay for 10us routine show below. DELAY10 ; burns 8 cycles + the call goto $+1 ; goto the next instruction call retlbl ; goto the next instruction retlbl return ; go back and burn 2 cycles for 10 cycles or 10us at 4Mhz and burn 2 cycles and burn 2 more cycles (actualy done 2x for 4 cycles consumed)
(c) 2002 Microchip Technology Inc.
DS80073F-page 15
PIC16F62X
5. Module: Data EEPROM The examples given in Section 13, concerning the Data EEPROM are incorrect. The EEPROM registers are all located in Bank 1. The examples show the registers in Bank 0 and Bank 1. The following code examples should be used instead to use this feature.
EXAMPLE 13-3:
DATA EEPROM VERIFY
EXAMPLE 13-1:
BSF MOVLW MOVWF BSF MOVF BCF
DATA EEPROM READ
; ; ; ; ; ; Bank 1 Address to read EE Read W = EEDATA Bank 0
STATUS, RP0 CONFIG_ADDR EEADR EECON1, RD EEDATA, W STATUS, RP0
; after the write in complete (i.e. in the write interrupt) BSF STATUS, RP0 ; Bank 1 MOVF EEDATA, W ; load the last written value into W BSF EECON1, RD ; start a read ; ; Is the value written (in W Reg) and ; read (in EEDATA) the same? ; SUBWF EEDATA, W ; the EEDATA has fresh data BTFSS STATUS, Z ; Is the Zero flag set? GOTO WRITE_ERR ; NO, Write Error ; YES, Good Write ; continue program
EXAMPLE 13-2:
DATA EEPROM WRITE
6.
Module: Comparator Under Section 9.5 Comparator Outputs, in the fourth sentence, "When the CM<2:0> = 110 or 001, multiplexors...", remove "or 001".
; set up the data and the address BSF STATUS, RP0 ; Bank 1 MOVLW CONFIG_ADDR ; MOVWF EEADR ; Address to write MOVLW CONFIG_DATA ; MOVWF EEDATA ; Data to write ; perform the write operation EECON1, WREN ; Enable Write INTCON, GIE ; Disable INTs 055h ; EECON2 ; Write 55 0AAh ; EECON2 ; Write AA EECON1, WR ; Set WR bit STATUS, RP0 ; Bank 0
BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BCF
DS80073F-page 16
(c) 2002 Microchip Technology Inc.
PIC16F62X
REVISION HISTORY
Rev A Document (6/00) Original errata document. Rev B Document (11/00) Issue 3 (CCP Compare Mode), Table 1 and 2 were added (page 2). Under the Clarifications/Corrections Section, Item 1, Table 15-12 was updated with additional information (page 3). Under the Clarifications/Corrections Section, the following Items were added: Rev C Document (6/01) Issues 2 and 3 were added. Under Clarifications/Corrections, Items 2 and 3 were changed and Item numbers were renumbered accordingly. Rev D Document (9/01) Item 3 was rewritten (page 9). Under the Clarifications/Corrections to the Data Sheet Section, the following items were changed: Item 2, Tables 17.1 and 17.2, were updated with minor changes (page 11 and page 12). Item 6 was added (page 16). Rev E Document (2/02) Item 4 was added, MCLR/RA5 in LVP mode (page 9). Rev F Document (4/02) Under Clarifications/Corrections, Item 2, Tables 17-1, 17.2 and 17.3 were updated with minor changes (pages 11, 12 and 13).
(c) 2002 Microchip Technology Inc.
DS80073F-page 17
PIC16F62X
NOTES:
DS80073F-page 18
(c) 2002 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro(R) MCUs. * * * The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet. The person doing so may be engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable". Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our product.
* * *
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, MXLAB, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
(c) 2002 Microchip Technology Inc.
DS80073F - page 19
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Japan
Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Rocky Mountain
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456
China - Beijing
Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Korea
Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
China - Fuzhou
Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
EUROPE
Denmark
Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai) Co., Ltd. Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 S. Albright Road Kokomo, Indiana 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Shenzhen
Microchip Technology Consulting (Shanghai) Co., Ltd., Shenzhen Liaison Office Rm. 1315, 13/F, Shenzhen Kerry Centre, Renminnan Lu Shenzhen 518001, China Tel: 86-755-2350361 Fax: 86-755-2366086
New York
150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335
Germany
Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
San Jose
Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Hong Kong SAR
Microchip Technology Hongkong Ltd. Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Italy
Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820
05/01/02
DS80073F-page 20
(c) 2002 Microchip Technology Inc.

▲Up To Search▲

Price & Availability of PIC16F62X02

	To Download PIC16F62X02 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .